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3:1 hdmi/dvi switch with equalization ADV3000 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 3 inputs, 1 output hdmi/dvi links enables hdmi 1.3-compliant receiver 4 tmds channels per link supports 250 mbps to 2.25 gbps data rates supports 25 mhz to 225 mhz pixel clocks equalized inputs for operatio n with long hdmi cables (20 meters at 2.25 gbps) fully buffered unidirectional inputs/outputs globally switchable, 50 on-chip terminations pre-emphasized outputs low added jitter single-supply operation (3.3 v) 4 auxiliary channels per link bidirectional unbuffered inputs/outputs flexible supply operation (3.3 v to 5 v) hdcp standard compatible allows switching of ddc bus and 2 additional signals output disable feature reduced power dissipation removable output termination allows building of larger arrays two ADV3000s support hdmi/dvi dual-link standards compatible: hdmi receiver, hdcp, dvi serial (i 2 c slave) and parallel control interface 80-lead, 14 mm 14 mm lqfp, pb-free package applications multiple input displays projectors a/v receivers set-top boxes advanced television (hdtv) sets ADV3000 hdmi receiver hdtv set dvd player 01: 18 namebrand power dv d set-top box game console 0 6712-001 figure 1. typical hdtv application functional block diagram low speed unbuffered high speed buffered avcc dvcc amuxvcc avee dvee vtto op[3:0] aux_com[3:0] on[3:0] + ? 4 bidirectional i2c_sda i2c_scl i2c_addr0 vtti vtti ip_a[3:0] in_a[3:0] + ? ip_b[3:0] in_b[3:0] + ? ip_c[3:0] in_c[3:0] aux_c[3:0] aux_b[3:0] aux_a[3:0] + ? 4 4 4 4 4 4 eq switch core switch core control logic config interface 2 2 serial parallel pp_ch[1:0] pp_ocl pp_eq pp_en pp_pre[1:0] reset pe 4 4 4 4 4 ADV3000 06712-002 figure 2. general description the ADV3000 is an hdmi?/dvi switch featuring equalized tmds inputs and pre-emphasized tmds? outputs, ideal for systems with long cable runs. outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-or technique. the ADV3000 is provided in an 80-lead lqfp, pb-free, surface- mount package, specified to operate over the ?40c to +85c temperature range. product highlights 1. supports data rates up to 2.25 gbps, enabling 1080p deep color (12-bit color) hdmi formats, and greater than uxga (1600 1200) dvi resolutions. 2. input cable equalizer enables use of long cables at the input (more than 20 meters of 24 awg cable at 2.25 gbps). 3. auxiliary switch routes a ddc bus and two additional signals for a single-chip, hdmi 1.3 receive-compliant solution.
ADV3000 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 maximum power dissipation ..................................................... 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 12 introduction ................................................................................ 12 input channels............................................................................ 12 output channels ........................................................................ 12 auxiliary switch.......................................................................... 13 serial control interface.................................................................. 14 reset ............................................................................................. 14 write procedure.......................................................................... 14 read procedure........................................................................... 15 switching/update delay ............................................................ 15 parallel control interface .............................................................. 16 serial interface configuration registers ..................................... 17 high speed device modes register......................................... 17 auxiliary device modes register............................................. 18 receiver settings register ......................................................... 18 input termination pulse register 1 and register 2 ............... 18 receive equalizer register 1 and register 2 ........................... 18 transmitter settings register.................................................... 18 parallel interface configuration registers .................................. 19 high speed device modes register......................................... 19 auxiliary device modes register............................................. 19 receiver settings register ......................................................... 20 input termination pulse register 1 and register 2 ............... 20 receive equalizer register 1 and register 2 ........................... 20 transmitter settings register.................................................... 20 application information................................................................ 21 pinout........................................................................................... 21 cable lengths and equalization............................................... 22 pcb layout guidelines.............................................................. 22 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 8/07revision 0: initial version
ADV3000 rev. 0 | page 3 of 28 specifications t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. table 1. parameter conditions/comments min typ max unit dynamic performance maximum data rate (dr) per channel nrz 2.25 gbps bit error rate (ber) prbs 2 23 ? 1 10 ?9 added deterministic jitter dr 2.25 gbps, prbs 2 7 ? 1, eq = 12 db 25 ps (p-p) added random jitter 1 ps (rms) differential intrapair sk ew at output 1 ps differential interpair skew 1 at output 40 ps equalization performance receiver (highest setting) 2 boost frequency = 825 mhz 12 db transmitter (highest setting) 3 boost frequency = 825 mhz 6 db input characteristics input voltage swing differential 150 1200 mv input common-mode voltage (v icm ) avcc ? 800 avcc mv output characteristics high voltage level single-ended high speed channel avcc ? 10 avcc + 10 mv low voltage level single-ended high speed channel avcc ? 600 avcc ? 400 mv rise/fall time (20% to 80%) 75 135 175 ps input termination resistance single-ended 50 auxiliary channels on resistance, r aux 100 on capacitance, c aux dc bias = 2.5 v, ac voltage = 3.5 v, f = 100 khz 8 pf input/output voltage range dvee amuxvcc v power supply avcc operating range 3 3.3 3.6 v quiescent current avcc outputs disabled 30 40 44 ma outputs enabled, no pre-emphasis 52 60 66 ma outputs enabled, maximum pre-emphasis 95 110 122 ma vtti input termination on 4 5 40 54 ma vtto output termination on, no pre-emphasis 35 40 46 ma output termination on, maximum pre-emphasis 72 80 90 ma dvcc 3.2 7 8 ma amuxvcc 0.01 0.1 ma power dissipation outputs disabled 115 271 361 mw outputs enabled, no pre-emphasis 384 574 671 mw outputs enabled, maximum pre-emphasis 704 910 1050 mw timing characteristics switching/update delay high speed switching register: hs_ch 200 ms all other configuration registers 1.5 ms reset pulse width 50 ns
ADV3000 rev. 0 | page 4 of 28 parameter conditions/comments min typ max unit serial control interface 5 input high voltage, v ih 2 v input low voltage, v il 0.8 v output high voltage, v oh 2.4 v output low voltage, v ol 0.4 v parallel control interface input high voltage, v ih 2 v input low voltage, v il 0.8 v 1 differential interpair skew is measured between the tmds pairs of a single link. 2 ADV3000 output meets the transmitter eye dia gram as defined in the dvi st andard revision 1.0 and the hdmi standard revision 1. 3. 3 cable output meets the receiver eye diagram mask as defined in the dvi standard revision 1.0 and the hdmi standard revision 1. 3. 4 typical value assumes only the selected hdmi/dvi link is active with nominal signal swings and that the unselected hdmi/dvi li nks are deactivated. minimum and maximum limits are measured at the respec tive extremes of input termination resistance and input voltage swing. 5 the ADV3000 is an i 2 c slave and its serial control i nterface is based on the 3.3 v i 2 c bus specification.
ADV3000 rev. 0 | page 5 of 28 absolute maximum ratings table 2. parameter rating avcc to avee 3.7 v dvcc to dvee 3.7 v dvee to avee 0.3 v vtti avcc + 0.6 v vtto avcc + 0.6 v amuxvcc 5.5 v internal power dissipation 2.2 w high speed input voltage avcc ? 1.4 v < v in < avcc + 0.6 v high speed differential input voltage 2.0 v low speed input voltage dvee ? 0.3 v < v in < amuxvcc + 0.6 v i 2 c? and parallel logic input voltage dvee ? 0.3 v < v in < dvcc + 0.6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions: a device soldered in a 4-layer jedec circuit board for surface-mount packages. jc is specified for no airflow. table 3. thermal resistance package type ja jc unit 80-lead lqfp 55 17.8 c/w maximum power dissipation the maximum power that can be safely dissipated by the ADV3000 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. te mporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. to ensure proper operation, it is necessary to observe the maximum power rating as determined by the coefficients in table 3 . esd caution
ADV3000 rev. 0 | page 6 of 28 pin configuration and fu nction descriptions ADV3000 top view (not to scale) 06712-003 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 17 18 19 20 11 59 58 57 54 55 56 60 53 52 51 49 48 47 46 45 44 43 42 41 50 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pin 1 aux_a0 aux_a1 aux_a2 aux_a3 dvee aux_b0 aux_b1 aux_b2 aux_b3 aux_com0 aux_com1 aux_com2 aux_com3 aux_c0 aux_c1 aux_c2 aux_c3 amuxvcc pp_eq pp_en avcc in_b0 ip_b0 in_b1 ip_b1 vtti in_b2 ip_b2 in_b3 ip_b3 in_a0 ip_a0 in_a1 ip_a1 vtti in_a2 ip_a2 in_a3 ip_a3 avee avcc ip_c3 in_c3 avee ip_c2 in_c2 vtti ip_c1 in_c1 avee ip_c0 in_c0 avcc avee vtti avcc avee i2c_sda i2c_scl pp_ocl i2c_addr0 dvee pp_ch0 pp_ch1 dvcc on0 op0 vtto on1 op1 dvcc on2 op2 vtto on3 op3 reset pp_pre0 pp_pre1 dvcc figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic type 1 description 1, 45, 48, 60 avcc power positive analog supply. 3.3 v nominal. 2 in_b0 hs i high speed input complement. 3 ip_b0 hs i high speed input. 4 in_b1 hs i high speed input complement. 5 ip_b1 hs i high speed input. 6, 15, 46, 54 vtti power input termination supply. nominally connected to avcc. 7 in_b2 hs i high speed input complement. 8 ip_b2 hs i high speed input. 9 in_b3 hs i high speed input complement. 10 ip_b3 hs i high speed input. 11 in_a0 hs i high speed input complement. 12 ip_a0 hs i high speed input. 13 in_a1 hs i high speed input complement. 14 ip_a1 hs i high speed input. 16 in_a2 hs i high speed input complement. 17 ip_a2 hs i high speed input. 18 in_a3 hs i high speed input complement. 19 ip_a3 hs i high speed input. 20, 44, 47, 51, 57 avee power negative analog supply. 0 v nominal. 21 i2c_addr0 control i 2 c address lsb. 22, 76 dvee power negative digital and auxiliary multiplexer power supply. 0 v nominal. 23 pp_ch0 control high speed source selection parallel interface lsb. 24 pp_ch1 control high speed source selection parallel interface msb.
ADV3000 rev. 0 | page 7 of 28 pin no. mnemonic type 1 description 25, 31, 40 dvcc power positive digital power supply. 3.3 v nominal. 26 on0 hs o high speed output complement. 27 op0 hs o high speed output. 28, 34 vtto power output termination supply. nominally connected to avcc. 29 on1 hs o high speed output complement. 30 op1 hs o high speed output. 32 on2 hs o high speed output complement. 33 op2 hs o high speed output. 35 on3 hs o high speed output complement. 36 op3 hs o high speed output. 37 reset control configuration registers reset. normally pulled up to avcc. 38 pp_pre0 control high speed pre-emphasis selection parallel interface lsb. 39 pp_pre1 control high speed pre-emphasis selection parallel interface msb. 40 dvcc power positive digital supply. 3.3 v nominal. 41 pp_ocl control high speed output current level parallel interface. 42 i2c_scl control i 2 c clock. 43 i2c_sda control i 2 c data. 49 in_c0 hs i high speed input complement. 50 ip_c0 hs i high speed input. 52 in_c1 hs i high speed input complement. 53 ip_c1 hs i high speed input. 55 in_c2 hs i high speed input complement. 56 ip_c2 hs i high speed input. 58 in_c3 hs i high speed input complement. 59 ip_c3 hs i high speed input. 61 pp_en control high speed output enable parallel interface. 62 pp_eq control high speed equalization selection parallel interface. 63 amuxvcc power positive auxiliary multiplexer supply. 5 v typical. 64 aux_c3 ls i/o low speed input/output. 65 aux_c2 ls i/o low speed input/output. 66 aux_c1 ls i/o low speed input/output. 67 aux_c0 ls i/o low speed input/output. 68 aux_com3 ls i/o low speed common input/output. 69 aux_com2 ls i/o low speed common input/output. 70 aux_com1 ls i/o low speed common input/output. 71 aux_com0 ls i/o low speed common input/output. 72 aux_b3 ls i/o low speed input/output. 73 aux_b2 ls i/o low speed input/output. 74 aux_b1 ls i/o low speed input/output. 75 aux_b0 ls i/o low speed input/output. 77 aux_a3 ls i/o low speed input/output. 78 aux_a2 ls i/o low speed input/output. 79 aux_a1 ls i/o low speed input/output. 80 aux_a0 ls i/o low speed input/output. 1 hs = high speed, ls = low speed, i = input, o = output.
ADV3000 rev. 0 | page 8 of 28 typical performance characteristics t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, unless otherwise noted. reference eye diagram at tp1 digital pattern generator ADV3000 evaluation board serial data analyzer sma coax cable hdmi cable 06712-004 tp1 tp2 tp3 figure 4. test circuit diagram for rx eye diagram 0.125ui/div at 2.25gbps 250mv/di v 06712-005 figure 5. rx eye diagram at tp2 (cable = 2 meters, 30 awg) 0.125ui/div at 2.25gbps 250mv/di v 06712-006 figure 6. rx eye diagram at tp2 (cable = 20 meters, 24 awg) 0.125ui/div at 2.25gbps 250mv/di v 06712-007 figure 7. rx eye diagram at tp3, eq = 6 db (cable = 2 meters, 30 awg) 0.125ui/div at 2.25gbps 250mv/di v 06712-008 figure 8. rx eye diagram at tp3, eq = 12 db (cable = 20 meters, 24 awg)
ADV3000 rev. 0 | page 9 of 28 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, unless otherwise noted. reference eye diagram at tp1 digital pattern generator sma coax cable hdmi cable tp1 tp2 tp3 ADV3000 evaluation board serial data analyzer 06712-009 figure 9. test circuit diagram for tx eye diagrams 0.125ui/div at 2.25gbps 250mv/di v 06712-010 figure 10. tx eye diagram at tp2, pe = 2 db 0.125ui/div at 2.25gbps 250mv/di v 06712-011 figure 11. tx eye diagram at tp2, pe = 6 db 0.125ui/div at 2.25gbps 250mv/di v 06712-012 figure 12. tx eye diagram at tp3, pe = 2 db (cable = 2 meters, 30 awg) 0.125ui/div at 2.25gbps 250mv/di v 06712-013 figure 13. tx diagram at tp3, pe = 6 db (cable = 10 meters, 28 awg)
ADV3000 rev. 0 | page 10 of 28 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, unless otherwise noted. 0.5 0.6 0 02 5 hdmi cable length (m) deterministic jitter (ui) 0.4 0.3 0.2 0.1 5 101520 2m cable = 30awg 5m to 20m cables = 24awg 1.65gbps eq = 12db 2.25gbps eq = 12db 2.25gbps eq = 6db 1.65gbps eq = 6db 06712-014 figure 14. jitter vs. input cable length (see figure 4 for test setup) 50 0 02 . 4 data rate (gbps) jitter (ps) 45 40 35 30 25 20 15 10 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 1080p 12-bit 1.65gbps eq = 12db 1080p 8-bit 1080i/720p 480i 480p dj (p-p) rj (rms) 06712-015 figure 15. jitter vs. data rate 50 0 3.0 3.6 supply voltage (v) jitter (ps) 45 40 35 30 25 20 15 10 5 3.1 3.2 3.3 3.4 3.5 rj (rms) dj (p-p) 06712-016 figure 16. jitter vs. supply voltage 0.5 0.6 0 02 0 hdmi cable length (m) deterministic jitter (ui) 0.4 0.3 0.2 0.1 2m cable = 30awg 5m to 20m cables = 24awg 51 01 5 1.65gbps, pe max 2.25gbps, pe max 1.65gbps, pe off 2.25gbps, pe off 06712-017 1200 0 0 data rate (gbps) eye height (mv) figure 17. jitter vs. output cable length (see figure 9 for test setup) 1000 800 600 400 200 2.4 06712-018 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 figure 18. eye height vs. data rate 800 0 2.5 3.6 supply voltage (v) eye height (mv) 700 600 500 400 300 200 100 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 06712-019 figure 19. eye height vs. supply voltage
ADV3000 rev. 0 | page 11 of 28 differential input swing (v) jitter (ps) t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, unless otherwise noted. 0 02 . 0 40 50 30 20 10 50 0 2.5 3.7 input common-mode voltage (v) jitter (ps) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 rj (rms) dj (p-p) 06712-020 figure 20. jitter vs. differential input swing 50 0 ?40 100 temperature (c) jitter (ps) 45 40 35 30 25 20 15 10 5 ?200 20406080 dj (p-p) rj (rms) 06712-021 figure 21. jitter vs. temperature 160 0 ?40 100 temperature (c) rise/fall time 20% to 80% (ps) 140 120 100 80 60 40 20 ?200 20406080 rise time fall time 06712-022 figure 22. rise and fall time vs. temperature 40 30 20 10 dj (p-p) 2.7 2.9 3.1 3.3 3.5 rj (rms) 06712-023 figure 23. jitter vs. input common-mode voltage 120 80 ?40 100 temperature (c) differential input termination resistance ( ? ) 115 110 105 100 95 90 85 ?200 20406080 06712-024 figure 24. differential input termination resistance vs. temperature
ADV3000 rev. 0 | page 12 of 28 theory of operation introduction the primary function of the ADV3000 is to switch one of three (hdmi or dvi) single-link sources to one output. each hdmi/ dvi link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. the high speed channels include a data-word clock and three transition minimized differential signaling (tmds) data channels run- ning at 10 the data-word clock frequency for data rates up to 2.25 gbps. the four low speed control signals are 5 v tolerant bidirectional lines that can carry configuration signals, hdcp encryption, and other information, depending upon the specific application. all four high speed tmds channels in a given link are identical; that is, the pixel clock can be run on any of the four tmds channels. transmit and receive channel compensation is provided for the high speed channels where the user can (manually) select among a number of fixed settings. the ADV3000 has two control interfaces. users have the option of controlling the part through either the parallel control interface or the i 2 c serial control interface. the ADV3000 has two user-programmable i 2 c slave addresses (one bit) to allow two ADV3000s to be controlled by a single i 2 c bus. a reset pin is provided to restore the control registers of the ADV3000 to default values. in all cases, serial programming values over- ride any prior parallel programming values and any use of the serial control interface disables the parallel control interface until the ADV3000 is reset. input channels each high speed input differential pair terminates to the 3.3 v vtti power supply through a pair of single-ended 50 on- chip resistors, as shown in figure 25 . the input terminations can be optionally disconnected for approximately 100 ms following a source switch. the user can program which of the 12 high speed input channels employs this feature by selectively programming the associated rx_pt bits in the input termination pulse register through the serial control interface. additionally, all the input terminations can be disconnected by programming the rx_to bit in the receiver settings register. by default, the input termination is enabled. the input terminations are enabled and cannot be switched off when programming the ADV3000 through the parallel control interface. cable eq 50? 50? ip_xx in_xx avee v tti 0 6712-035 figure 25. high speed input simplified schematic the input equalizer can be manually configured to provide two different levels of high frequency boost: 6 db or 12 db. the user can individually control the equalization level of all high speed input channels by selectively programming the associated rx_eq bits in the receive equalizer register through the serial control interface. alternately, the user can globally control the equaliza- tion level of all eight high speed input channels by setting the pp_eq pin of the parallel control interface. no specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the ADV3000 can be set to 12 db without degrading the signal integrity, even for short input cables. at the 12 db setting, the ADV3000 can equalize more than 20 meters of 24 awg cable at 2.25 gbps. output channels each high speed output differential pair is terminated to the 3.3 v vtto power supply through two 50 on-chip resistors (see figure 26 ). this termination is user-selectable; it can be turned on or off by programming the tx_pto bit of the transmitter settings register through the serial control interface. the output termination resistors of the ADV3000 back-terminate the output tmds transmission lines. these back-terminations, as recommended in the hdmi 1.3 specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the ADV3000 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal. the ADV3000 output has a disable feature that places the outputs in an inactive mode. this mode is enabled by programming the hs_en bit of the high speed device modes register through the serial control interface or by setting the pp_en pin of the parallel control interface. larger wire-ored arrays can be constructed using the ADV3000 in this mode. v tto 50? 50? opx onx avee disable i out 0 6712-025 figure 26. high speed output simplified schematic
ADV3000 rev. 0 | page 13 of 28 the ADV3000 requires output termination resistors when the high speed outputs are enabled. termination can be internal and/or external. the internal terminations of the ADV3000 are enabled by programming the tx_pto bit of the transmitter settings register. these terminations are always enabled in parallel control mode. external terminations can be provided either by on-board resistors or by the input termination resistors of an hdmi/ dvi receiver. if both the internal terminations are enabled and external terminations are present, set the output current level to 20 ma by programming the tx_ocl bit of the transmitter settings register through the serial control interface or by setting the pp_ocl pin of the parallel control interface. the output current level defaults to the level indicated by pp_ocl upon reset. if only external terminations are provided (if the internal terminations are disabled), set the output current level to 10 ma by programming the tx_ocl bit of the transmitter settings register or by setting the pp_ocl pin of the parallel control interface. the high speed outputs must be disabled if there are no output termination resistors present in the system. the output pre-emphasis can be manually configured to provide one of four different levels of high frequency boost. the specific boost level is selected by programming the tx_pe bits of the transmitter settings register through the serial control interface, or by setting the pp_pe bus of the parallel control interface. no specific cable length is suggested for a particular pre-emphasis setting because cable performance varies widely between manufacturers. auxiliary switch the auxiliary (low speed) lines have no amplification. they are routed using a passive switch that is bandwidth compatible with standard speed i 2 c. the schematic equivalent for this passive connection is shown in figure 27 . aux_com0 aux_a0 ?c aux ?c aux r aux 06712-026 figure 27. auxiliary channel simplified schematic, aux_a0 to aux_com0 routing example when turning off the ADV3000, care needs to be taken with the amuxvcc supply to ensure that the auxiliary multiplexer pins remain in a high impedance state. a scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel (ddc) bus. in some applica- tions, additional devices can be connected to the ddc bus (such as an eeprom with edid information) upstream of the ADV3000. extended display identification data (edid) is a vesa standard-defined data format for conveying display configuration information to sources to optimize display use. edid devices may need to be available via the ddc bus, regard- less of the state of the ADV3000 and any downstream circuit. for this configuration, the auxiliary inputs of the powered down ADV3000 need to be in a high impedance state to avoid pulling down on the ddc lines and preventing these other devices from using the bus. when the ADV3000 is powered from a simple resistor network, as shown in figure 28 , it uses the 5 v supply that is required from any hdmi/dvi source to guarantee high impedance of the auxiliary multiplexer pins. the amuxvcc supply does not draw any static current; therefore, it is recommended that the resistor network tap the 5 v supplies as close to the connectors as possible to avoid any additional voltage drop. this precaution does not need to be taken if the ddc peripheral circuitry is connected to the bus downstream of the ADV3000. peripheral circuitry +5v source c pin 18 hdmi connector pin 14 dvi connector 10k ? 10m ? i<50ma peripheral circuitry peripheral circuitry source a +5v source b +5v pin 18 hdmi connector pin 14 dvi connector pin 18 hdmi connector pin 14 dvi connector 10k? 10k? i<50ma i<50ma amuxvcc ADV3000 +5v internal (if any) 0 6712-027 figure 28. suggested amuxvcc power scheme
ADV3000 rev. 0 | page 14 of 28 serial control interface reset on initial power-up, or at any point in operation, the ADV3000 register set can be restored to preprogrammed default values by pulling the reset pin to low in accordance with the specifica- tions in table 1 . during normal operation, however, the reset pin must be pulled up to 3.3 v. following a reset, the prepro- grammed default values of the ADV3000 register set correspond to the state of the parallel interface configuration registers, as listed in table 18 . the ADV3000 can be controlled through the parallel control interface until the first serial control event occurs. as soon as any serial control event occurs, the serial programming values, corresponding to the state of the serial interface configuration registers ( table 5 ), override any prior parallel programming values, and the parallel control interface is disabled until the part is subsequently reset. write procedure to write data to the ADV3000 register set, an i 2 c master (such as a microcontroller) needs to send the appropriate control signals to the ADV3000 slave device. the signals are controlled by the i 2 c master, unless otherwise specified. for a diagram of the procedure, see figure 29 . the steps for a write procedure are as follows: 1. send a start condition (while holding the i2c_scl line high, pull the i2c_sda line low). 2. send the ADV3000 part address (seven bits). the upper six bits of the ADV3000 part address are the static value [100100] and the lsb is set by input pin i2c_addr0. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the ADV3000 to acknowledge the request. 5. send the register address (eight bits) to which data is to be written. this transfer should be msb first. 6. wait for the ADV3000 to acknowledge the request. 7. send the data (eight bits) to be written to the register whose address was set in step 5. this transfer should be msb first. 8. wait for the ADV3000 to acknowledge the request. 9. perform one of the following: 9a. send a stop condition (while holding the i2c_scl line high, pull the i2c_sda line high) and release control of the bus to end the transaction (shown in figure 29 ). 9b. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 2 in this procedure to perform another write. 9c. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 2 of the read procedure (in the read procedure section) to perform a read from another address. 9d. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 8 of the read procedure (in the read procedure section) to perform a read from the same address set in step 5. r/w ack ack start fixed part addr register addr data stop ack 1 2 3 4 5 6 7 8 9 i2c_scl general case i2c_sda example i2c_sda *the switching/update delay begins at the falling edge of the last data bit; for example, the falling edge just before step 8. * 06712-028 i2c_addr0 figure 29. i 2 c write diagram
ADV3000 rev. 0 | page 15 of 28 start fixed part addr register addr fixed part addr data stop ack i2c_addr0 ack r/w addr ack ack r/w sr 1 2 3 4 5 6 7 8 9 10 11 12 13 i2c_scl general case i2c_sda example i2c_sda 06712-029 figure 30. i 2 c read diagram read procedure to read data from the ADV3000 register set, an i 2 c master (such as a microcontroller) needs to send the appropriate control signals to the ADV3000 slave device. the signals are controlled by the i 2 c master, unless otherwise specified. for a diagram of the procedure, see figure 30 . the steps for a read procedure are as follows: 1. send a start condition (while holding the i2c_scl line high, pull the i2c_sda line low). 2. send the ADV3000 part address (seven bits). the upper six bits of the ADV3000 part address are the static value [100100] and the lsb is set by input pin i2c_addr0. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the ADV3000 to acknowledge the request. 5. send the register address (eight bits) from which data is to be read. this transfer should be msb first. 6. wait for the ADV3000 to acknowledge the request. 7. send a repeated start condition (sr) by holding the i2c_scl line high and pulling the i2c_sda line low. 8. resend the ADV3000 part address (seven bits) from step 2. the upper six bits of the ADV3000 part address are the static value [100100] and the lsb is set by the input pin i2c_addr0. this transfer should be msb first. 9. send the read indicator bit (1). 10. wait for the ADV3000 to acknowledge the request. 11. the ADV3000 serially transfers the data (eight bits) held in the register indicated by the address set in step 5. this data is sent msb first. 12. acknowledge the data from the ADV3000. 13. perform one of the following: 13a. s op condition (while holding the i2c_scl line high, pull the sda line high) and release control of the bus to end the transaction (shown in end a st ). 13b. ted start condition (while holding the 13c. 13d. on (while holding the switch writes to the configura- s update ally y figure 30 send a repea i2c_scl line high, pull the i2c_sda line low) and continue with step 2 of the write procedure (previous wr ite pro cedure section) to perform a write. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 2 of this procedure to perform a read from another address. send a repeated start conditi i2c_scl line high, pull the i2c_sda line low) and continue with step 8 of this procedure to perform a read from the same address. ing/update delay there is a delay between when a user tion registers of the ADV3000 and when that state change take physical effect. this update delay occurs regardless of whether the user programs the ADV3000 via the serial or the parallel control interface. when using the serial control interface, the update delay begins at the falling edge of i2c_scl for the last data bit transferred, as shown in figure 29 . when using the parallel control interface, the update delay begins at the transition edge of the relevant parallel interface pin. this delay is register specific and the times are specified in table 1 . during a delay window, new values can be written to the configuration registers, but the ADV3000 does not physic update until the end of the delay window of that register. writing new values during the delay window does not reset the window; new values supersede the previously written values. at the end of the delay window, the ADV3000 physically assumes the state indicated by the last set of values written to the configuration registers. if the configuration registers are written after the dela window ends, the ADV3000 immediately updates and a new delay window begins.
ADV3000 rev. 0 | page 16 of 28 parallel control interface the ADV3000 can be controlled through the parallel interface using the pp_en, pp_ch[1:0], pp_eq, pp_pre[1:0], and pp_ocl pins. logic levels for the parallel interface pins are set in accordance with the specifications listed in table 1 . setting these pins updates the parallel control interface registers, as listed in table 18 . following a reset, the ADV3000 can be controlled through the parallel control interface until the first serial control event occurs. as soon as any serial control event occurs, the serial programming values override any prior parallel programming values, and the parallel control interface is disabled until the part is subsequently reset. the default serial programming values correspond to the state of the serial interface configuration registers, as listed in table 5 .
ADV3000 rev. 0 | page 17 of 28 serial interface configuration registers the serial interface configuration registers can be read and written using the i 2 c serial control interface, pin i2c_sda, and pin i2c_scl. the least significant bit of the ADV3000 i 2 c part address is set by tying pin i2c_addr0 to 3.3 v (logic 1) or 0 v (logic 0). as soon as the serial control interface is used, the parallel control interface is disabled until the ADV3000 is reset as described in the serial control interface section. table 5. serial (i 2 c) interface register map name it 7 it 6 it 5 it 4 it 3 it 2 it 1 it 0 addr. default high speed switch enable high speed switching mode select high speed source select high speed device modes hs_en 0 0 0 0 hs_ch[1] hs_ch[0] 0x00 0x40 auxiliary switch enable auxiliary switch source select auxiliary device modes aux_en 0 0 0 0 aux_ch[1] aux_ch[0] 0x01 0x40 high speed input termination select receiver settings rx_to 0x10 0x01 source a and source b : input termination pulse-on-source switch select (disconnect termination for a short period of time) input termination pulse 1 rx_pt[7] rx_pt[6] rx_pt[5] rx_pt[4] rx_pt[3] rx_pt[2] rx_pt[1] rx_pt [0] 0x11 0x00 source c: input termination pulse-on-source switch select (disconnect termination for a short period of time) input termination pulse 2 0 0 0 0 rx_pt[11] rx_pt[10] rx_pt[9] rx_pt[8] 0x12 0x00 source a and source b: input equalization level select receive equalizer 1 rx_eq[7] rx_eq[6] rx_eq[5] rx_eq[4] rx_eq[3] rx_eq[2] rx_eq[1] rx_eq[0] 0x13 0x00 source c input equalization level select receive equalizer 2 0 0 0 0 rx_eq[11] rx_eq[10] rx_eq[9] rx_eq[8] 0x14 0x00 high speed output pre-emphasis level select high speed output termination select high speed output current level select transmitter settings tx_pe[1] tx_pe[0] tx_pto tx_ocl 0x20 0x03 high speed device modes register hs_en: high speed (tmds) channels enable bit table 6. hs_en description hs_en description 0 high speed channels off, low power/standby mode 1 high speed channels on hs_ch[1:0]: high speed (tmds) switch source select bus table 7. hs_en mapping hs_ch[1:0] o[3:0] description 00 a[3:0] high speed source a switched to output 01 b[3:0] high speed source b switched to output 10 c[3:0] high speed source c switched to output 11 illegal value
ADV3000 rev. 0 | page 18 of 28 auxiliary device modes register aux_en: auxiliary (low speed) switch enable bit table 8. aux_en description aux_en description 0 auxiliary switch off, no low speed input/output to low speed common input/output connection 1 auxiliary switch on aux_ch[1:0]: auxiliary (low speed) switch source select bus table 9. aux_ch mapping aux_ch[1:0] aux_com[3:0] description 00 aux_a[3:0] auxiliary source a switched to output 01 aux_b[3:0] auxiliary source b switched to output 10 aux_c[3:0] auxiliary source c switched to output 11 illegal value receiver settings register rx_to: high speed (tmds) channels input termination on/off select bit table 10. rx_to description rx_to description 0 input termination off 1 input termination on (can be pulsed on and off accord- ing to settings in the input termination pulse register) input termination pulse register 1 and register 2 rx_pt[x]: high speed (tmds) input channel x pulse-on-source switch select bit table 11. rx_pt[x] description rx_pt[x] description 0 input termination for tmds channel x always connected when source is switched 1 input termination for tmds channel x disconnected for 100 ms when source switched table 12. rx_pt[x] mapping rx_pt[x] corresponding input tmds channel bit 0 b0 bit 1 b1 bit 2 b2 bit 3 b3 bit 4 a0 bit 5 a1 bit 6 a2 bit 7 a3 bit 8 c3 bit 9 c2 bit 10 c1 bit 11 c0 receive equalizer register 1 and register 2 rx_eq[x]: high speed (tmds) input x equalization level select bit table 13. rx_eq[x] description rx_eq[x] description 0 low equalization (6 db) 1 high equalization (12 db) table 14. rx_eq[x] mapping rx_eq[x] corresponding input tmds channel bit 0 b0 bit 1 b1 bit 2 b2 bit 3 b3 bit 4 a0 bit 5 a1 bit 6 a2 bit 7 a3 bit 8 c3 bit 9 c2 bit 10 c1 bit 11 c0 transmitter settings register tx_pe[1:0]: high speed (tmds) output pre-emphasis level select bus (for all tmds channels) table 15. tx_pe[1:0] description tx_pe[1:0] description 00 no pre-emphasis (0 db) 01 low pre-emphasis (2 db) 10 medium pre-emphasis (4 db) 11 high pre-emphasis (6 db) tx_pto: high speed (tmds) output termination on/off select bit (for all channels) table 16. tx_pto description tx_pto description 0 output termination off 1 output termination on tx_ocl: high speed (tmds) output current level select bit (for all channels) table 17. tx_ocl description tx_ocl description 0 output current set to 10 ma 1 output current set to 20 ma
ADV3000 rev. 0 | page 19 of 28 parallel interface configuration registers the parallel interface configuration registers can be directly set using the pp_en, pp_ch[1:0], pp_eq, pp_pre[1:0], and pp_ocl pins. this interface is only accessible after the part is reset and before any registers are accessed using the serial control interf ace. the state of each pin is set by tying it to 3.3 v (logic 1) or 0 v (logic 0). table 18. parallel interface register map name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high speed switch enable high speed source select high speed device modes pp_en 0 0 0 0 pp_ch[1] pp_ch[0] auxiliary switch enable auxiliary switch source select auxiliary device modes 1 0 0 0 0 pp_ch[1] pp_ch[0] input termination on/off select (termination always on) receiver settings 1 source a and source b input termination pulse-on- source switch select (termination always on) input termination pulse 1 0 0 0 0 0 0 0 0 source c input termination pulse-on-source switch select (termination always on) input termination pulse 2 0 0 0 0 0 0 0 0 source a and source b input equalization level select receive equalizer 1 pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq source c input equalization level select receive equalizer 2 pp_eq pp_eq pp_eq pp_eq output pre-emphasis level select output current level select transmitter settings pp_pe[1] pp_pe[0] pp_ocl high speed device modes register pp_en: high speed (tmds) channels enable bit table 19. pp_en description pp_en description 0 high speed channels off, low power/standby mode 1 high speed channels on pp_ch[1:0]: high speed (tmds) switch source select bus table 20. high speed switch mode mapping pp_ch[1:0] o[3:0] description 00 a[3:0] high speed source a switched to output 01 b[3:0] high speed source b switched to output 10 c[3:0] high speed source c switched to output 11 illegal value auxiliary device modes register the auxiliary (low speed) switch is always enabled when using the parallel interface. pp_ch[1:0]: auxiliary switch source select bus table 21. auxiliary switch mode mapping pp_ch[1:0] aux_com[3:0] description 00 aux_a[3:0] auxiliary source a switched to output 01 aux_b[3:0] auxiliary source b switched to output 10 aux_c[3:0] auxiliary source c switched to output 11 illegal value
ADV3000 rev. 0 | page 20 of 28 receiver settings register high speed (tmds) channels input termination is fixed to on when using the parallel interface. input termination pulse register 1 and register 2 high speed input (tmds) channels pulse-on-source switching fixed to off when using the parallel interface. receive equalizer register 1 and register 2 pp_eq: high speed (tmds) inputs equalization level select bit (for all tmds input channels) the input equalization cannot be set individually (per channel) when using the parallel interface; one equalization setting affects all input channels. table 22. pp_eq description pp_eq description 0 low equalization (6 db) 1 high equalization (12 db) transmitter settings register pp_pe[1:0]: high speed (tmds) output pre-emphasis level select bus (for all tmds channels) table pp_pe[1:0] description pp_pe[1:0] description 00 no pre-emphasis (0 db) 01 low pre-emphasis (2 db) 10 medium pre-emphasis (4 db) 11 high pre-emphasis (6 db) pp_ocl: high speed (tmds) output current level select bit (for all tmds channels) table tx_ocl description pp_ocl description 0 output current set to 10 ma 1 output current set to 20 ma
ADV3000 rev. 0 | page 21 of 28 application information 0 6712-036 figure 31. layout of the tmds traces on the ADV3000 evaluation board (only top signal routing layer is shown) the ADV3000 is an hdmi/dvi switch, featuring equalized tmds inputs and pre-emphasized tmds outputs. it is intended for use as a 3:1 switch in systems with long cable runs on both the input and/or the output, and is fully hdmi 1.3 receive- compliant. pinout the ADV3000 is designed to have an hdmi/dvi receiver pinout at its input and a transmitter pinout at its output. this makes the ADV3000 ideal for use in avr-type applications where a designer routes both the inputs and the outputs directly to hdmi/dvi connectors, as shown in figure 31 . when the ADV3000 is used in receiver type applications, it is necessary to change the order of the output pins on the pcb to align with the on-board receiver. one advantage of the ADV3000 in an avr-type application is that all of the high speed signals can be routed on one side (the topside) of the board, as shown in figure 31 . in addition to 12 db of input equalization, the ADV3000 provides up to 6 db of output pre-emphasis that boosts the output tmds signals and allows the ADV3000 to precompensate when driving long pcb traces or output cables. the net effect of the input equalization and output pre-emphasis of the ADV3000 is that the ADV3000 can compensate for the signal degradation of both input and output cables; it acts to reopen a closed input data eye and transmit a full swing hdmi signal to an end receiver. more information on the specific performance metrics of the ADV3000 can be found in the typical performance characteristics section. the ADV3000 also provides a distinct advantage in receive-type applications because it is a fully buffered hdmi/dvi switch. although inverting the output pin order of the ADV3000 on the pcb requires a designer to place vias in the high speed signal path, the ADV3000 fully buffers and electrically decouples the outputs from the inputs. therefore, the effects of the vias placed on the output signal lines are not seen at the input of the ADV3000. the programmable output terminations also improve signal quality at the output of the ADV3000. the pcb designer therefore has significantly improved flexibility in the placement and routing of the output signal path with the ADV3000 over other solutions.
ADV3000 rev. 0 | page 22 of 28 cable lengths and equalization the ADV3000 offers two levels of programmable equalization for the high speed inputs: 6 db and 12 db. the equalizer of the ADV3000 supports video data rates of up to 2.25 gbps, and as shown in figure 14 , it can equalize more than 20 meters of 24 awg hdmi cable at 2.25 gbps, which corresponds to the video format, 1080p with deep color. the length of cable that can be used in a typical hdmi/dvi application depends on a large number of factors, including: ? cable quality: the quality of the cable in terms of conductor wire gauge and shielding. thicker conductors have lower signal degradation per unit length. ? data rate: the data rate being sent over the cable. the signal degradation of hdmi cables increases with data rate. ? edge rates: the edge rates of the source input. slower input edges result in more significant data eye closure at the end of a cable. ? receiver sensitivity: the sensitivity of the terminating receiver. as such, specific cable types and lengths are not recommended for use with a particular equalizer setting. in nearly all applica- tions, the ADV3000 equalization level can be set to high, or 12 db, for all input cable configurations at all data rates, without degrading the signal integrity. pcb layout guidelines the ADV3000 is used to switch two distinctly different types of signals, both of which are required for hdmi and dvi video. these signal groups require different treatment when laying out a pc board. the first group of signals carries the audiovisual (av) data. hdmi/ dvi video signals are differential, unidirectional, and high speed (up to 2.25 gbps). the channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating at the maximum specified system data rate. it is especially important to note that the differential traces that carry the tmds signals should be designed with a controlled differential impedance of 100 . the ADV3000 provides single- ended, 50 terminations on-chip for both its inputs and outputs, and both the input and output terminations can be enabled or disabled through the serial control interface. the output terminations can also be enabled or disabled through the parallel control interface. transmitter termination is not required by the hdmi 1.3 standard, but its inclusion improves the overall system signal integrity. the audiovisual (av) data carried on these high speed channels is encoded by a technique called transmission minimized differ- ential signaling (tmds) and in the case of hdmi, is also encrypted according to the high bandwidth digital copy protection (hdcp) standard. the second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink. depending upon the application, these signals can include the ddc bus (this is an i 2 c bus used to send edid information and hdcp encryption keys between the source and the sink), the consumer electronics control (cec) line, and the hot plug detect (hpd) line. these auxiliary signals are bidirectional, low speed, and transferred over a single-ended transmission line that does not need to have controlled impedance. the primary concern with laying out the auxiliary lines is ensuring that they conform to the i 2 c bus standard and do not have excessive capacitive loading. tmds signals in the hdmi/dvi standard, four differential pairs carry the tmds signals. in dvi, three of these pairs are dedicated to carrying rgb video and sync data. for hdmi, audio data is interleaved with the video data; the dvi standard does not incorporate audio information. the fourth high speed differ- ential pair is used for the av data-word clock, and runs at one-tenth the speed of the tmds data channels. the four high speed channels of the ADV3000 are identical. no concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any tmds signal. the user chooses which signal is routed over which channel. additionally, the tmds channels are symmetrical; therefore, the p and n of a given differential pair are inter- changeable, provided the inversion is consistent across all inputs and outputs of the ADV3000. however, the routing between inputs and outputs through the ADV3000 is fixed. for example, output channel 0 always switches between input a0, input b0, input c0, and so forth. the ADV3000 buffers the tmds signals and the input traces can be considered electrically independent of the output traces. in most applications, the quality of the signal on the input tmds traces is more sensitive to the pcb layout. regardless of the data being carried on a specific tmds channel, or whether the tmds line is at the input or the output of the ADV3000, all four high speed signals should be routed on a pcb in accordance with the same rf layout guidelines. layout for the tmds signals the tmds differential pairs can be either microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. if microstrip traces are used, there should be a continuous reference plane on the pcb layer directly below the traces. if stripline traces are used, they must be sandwiched between two continuous reference planes in the pcb stack-up. additionally, the p and n of each differential pair must have a controlled differential impedance of 100 . the characteristic impedance of a differential pair is a function of several variables including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the pc board binder material. interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path, therefore, it is preferable to route the tmds lines exclusively on one layer of the
ADV3000 rev. 0 | page 23 of 28 board, particularly for the input traces. in some applications, such as using multiple ADV3000s to construct large input arrays, the use of interlayer vias becomes unavoidable. in these situations, the input termination feature of the ADV3000 improves system signal integrity by absorbing reflections. take care to use vias minimally and to place vias symmetrically for each side of a given differential pair. furthermore, to prevent unwanted signal coupling and interference, route the tmds signals away from other signals and noise sources on the pcb. both traces of a given differential pair must be equal in length to minimize intrapair skew. maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (dcd). the p and n of a given differential pair should always be routed together to establish the required 100 differ- ential impedance. enough space should be left between the differential pairs of a given group so that the n of one pair does not couple to the p of another pair. for example, one technique is to make the interpair distance 4 to 10 times wider than the intrapair spacing. any group of four tmds channels (input a, input b, input c, or the output) should have closely matched trace lengths to minimize interpair skew. severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. a good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on fr4 material. minimizing intrapair and interpair skew becomes increasingly important as data rates increase. any introduced skew consti- tutes a correspondingly larger fraction of a bit period at higher data rates. though the ADV3000 features input equalization and output pre-emphasis, the length of the tmds traces should be mini- mized to reduce overall signal degradation. commonly used pcb material such as fr4 is lossy at high frequencies; therefore, long traces on the circuit board increase signal attenuation resulting in decreased signal swing and increased jitter through intersymbol interference (isi). controlling the characterist ic impedance of a tmds differential pair the characteristic impedance of a differential pair depends on a number of variables, including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the pcb binder material. to a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. there are many combinations that can produce the correct characteristic impedance. generally, working with the pcb fabricator is required to obtain a set of parameters to produce the desired results. one consideration is how to guarantee a differential pair with a differential impedance of 100 over the entire length of the trace. one technique to accomplish this is to change the width of the traces in a differential pair based on how closely one trace is coupled to the other. when the two traces of a differential pair are close and strongly coupled, they should have a width that produces a 100 differential impedance. when the traces split apart, to go into a connector, for example, and are no longer so strongly coupled, the width of the traces should be increased to yield a differential impedance of 100 in the new configuration. ground current return in some applications, it can be necessary to invert the output pin order of the ADV3000. this requires a designer to route the tmds traces on multiple layers of the pcb. when routing differential pairs on multiple layers, it is also necessary to reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals. standard plated through-hole vias are acceptable for both the tmds traces and the reference plane. an example of this is illustrated in figure 32 . pcb dielectric silkscreen silkscreen pcb dielectric pcb dielectric layer 2: gnd (reference plane) layer 4: signal (microstrip) through-hole vias layer 1: signal (microstrip) keep reference plane adjacent to signal on all layers to provide continuous ground current return path. layer 3: pwr (reference plane) 06712-031 figure 32. example routing of reference plane tmds terminations the ADV3000 provides internal, 50 single-ended terminations for all of its high speed inputs and outputs. it is not necessary to include external termination resistors for the tmds differential pairs on the pcb. the output termination resistors of the ADV3000 back-terminate the output tmds transmission lines. these back-terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the ADV3000 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal.
ADV3000 rev. 0 | page 24 of 28 auxiliary control signals there are four single-ended control signals associated with each source or sink in an hdmi/dvi application. these are hot plug detect (hpd), consumer electronics control (cec), and two display data channel (ddc) lines. the two signals on the ddc bus are sda and scl (serial data and serial clock, respectively). these four signals can be switched through the auxiliary bus of the ADV3000 and do not need to be routed with the same strict considerations as the high speed tmds signals. in general, it is sufficient to route each auxiliary signal as a single-ended trace. these signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the pcb. however, it is best to follow strict layout practices whenever possible to prevent the pcb design from affecting the overall application. the specific routing of the hpd, cec, and ddc lines depends upon the application in which the ADV3000 is being used. for example, the maximum speed of signals present on the auxiliary lines is 100 khz i 2 c data on the ddc lines; therefore, any layout that enables 100 khz i 2 c to be passed over the ddc bus should suffice. the hdmi 1.3 specification, however, places a strict 50 pf limit on the amount of capacitance that can be measured on either sda or scl at the hdmi input connector. this 50 pf limit includes the hdmi connector, the pcb, and whatever capacitance is seen at the input of the ADV3000, or an equivalent receiver. there is a similar limit of 100 pf of input capacitance for the cec line. the parasitic capacitance of traces on a pcb increases with trace length. to help ensure that a design satisfies the hdmi specification, the length of the cec and ddc lines on the pcb should be made as short as possible. additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the pcb stackup, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance. an example of the board stackup is shown in figure 33 . pcb dielectric layer 1: signal (microstrip) silkscreen silkscreen pcb dielectric pcb dielectric layer 2: gnd (reference plane) layer 3: pwr (reference plane) layer 4: signal (microstrip) w 3w 3w reference layer relieved underneath microstrip 06712-032 figure 33. example board stackup hpd is a dc signal presented by a sink to a source to indicate that the source edid is available for reading. the placement of this signal is not critical, but it should be routed as directly as possible. when the ADV3000 is powered up, one set of the auxiliary inputs is passively routed to the outputs. in this state, the ADV3000 looks like a 100 resistor between the selected auxiliary inputs and the corresponding outputs as illustrated in figure 27 . the ADV3000 does not buffer the auxiliary signals, therefore, the input traces, output traces, and the connection through the ADV3000 all must be considered when designing a pcb to meet hdmi/dvi specifications. the unselected auxiliary inputs of the ADV3000 are placed into a high impedance mode when the device is powered up. to ensure that all of the auxiliary inputs of the ADV3000 are in a high impedance mode when the device is powered off, it is necessary to power the amuxvcc supply as illustrated in figure 28 . in contrast to the auxiliary signals, the ADV3000 buffers the tmds signals, allowing a pcb designer to layout the tmds inputs independently of the outputs. power supplies the ADV3000 has five separate power supplies referenced to two separate grounds. the supply/ground pairs are: ? avc c /avee ? vtti/avee ? vtto/avee ? dvcc/dvee ? amuxvcc/dvee the avcc/avee (3.3 v) and dvcc/dvee (3.3 v) supplies power the core of the ADV3000. the vtti/avee supply (3.3 v) powers the input termination (see figure 25 ). similarly, the vtto/avee supply (3.3 v) powers the output termination (see figure 26 ). the amuxvcc/dvee supply (3.3 v to 5 v) powers the auxiliary multiplexer core and determines the maxi- mum allowed voltage on the auxiliary lines. for example, if the ddc bus is using 5 v i 2 c, then amuxvcc should be connected to +5 v relative to dvee. in a typical application, all pins labeled avee or dvee should be connected directly to ground. all pins labeled avcc, dvcc, vtti, or vtto should be connected to 3.3 v, and pin amuxvcc tied to 5 v. the supplies can also be powered individually, but care must be taken to ensure that each stage of the ADV3000 is powered correctly.
ADV3000 rev. 0 | page 25 of 28 power supply bypassing the ADV3000 requires minimal supply bypassing. when powering the supplies individually, place a 0.01 f capacitor between each 3.3 v supply pin (avcc, dvcc, vtti, and vtto) and ground to filter out supply noise. generally, bypass capacitors should be placed near the power pins and should connect directly to the relevant supplies (without long intervening traces). for example, to improve the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias as shown in figure 34 . extra added inductance recommended not recommended 06712-033 figure 34. recommended pad outline for bypass capacitors in applications where the ADV3000 is powered by a single 3.3 v supply, it is recommended to use two reference supply planes and bypass the 3.3 v reference plane to the ground reference plane with one 220 pf, one 1000 pf, two 0.01 f, and one 4.7 f capacitors. the capacitors should via down directly to the supply planes and be placed within a few centimeters of the ADV3000. the amuxvcc supply does not require additional bypassing. this bypassing scheme is illustrated in figure 35 . 06712-038 ADV3000 decouplin g capacitors auxiliary lines tmds traces figure 35. example placement of power supply decoupling capacitors around the ADV3000
ADV3000 rev. 0 | page 26 of 28 outline dimensions compliant to jedec standards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 top view (pins down) pin 1 051706-a figure 36. 80-lead low profile quad flat package [lqfp] (st-80-2) dimensions shown in millimeters ordering guide model temperature range package descript ion package option ordering quantity ADV3000astz 1 ?40c to +85c 80-lead low profile quad flat package [lqfp] st-80-2 ADV3000astz-rl 1 ?40c to +85c 80-lead low profile quad flat package [lqfp], reel st-80-2 1,000 ADV3000-evalz 1 evaluation board 1 z = rohs compliant part.
ADV3000 rev. 0 | page 27 of 28 notes
ADV3000 rev. 0 | page 28 of 28 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06712-0-8/07(0)

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